VCE IB parser lacks per-field dword bounds, enabling OOB read (pass 1) and OOB write (pass 2) into shared SA BO pool
Summary
amdgpu_vce.c:724/790/954 loop for(idx=0;idx<length_dw). Only idx bounded; ptr[idx+N] for N up to 12 never validated against length_dw. Pass 2 amdgpu_set_ib_value at 656-657 writes lo/hi back into ib->ptr[lo]/[hi] which can be OOB. IB carved from SA pool exactly ib_bytes; adjacent SA BO is another users IB. OOB read in pass 1 feeds amdgpu_cs_find_mapping. Groomed SA pool -> cross-user IB relocation overwrite. Fix: idx+len/4<=length_dw check + bounds-check lo/hi in cs_reloc.
Discussion (0)
PoC verification
Evidence pack
findings/poc/DF-1626 Β· 4 files| File | Type | Description | Size | |
|---|---|---|---|---|
| VERDICT.md | verdict | source-only confirmation + mechanism + fix | 1.6 KB | β raw |
| fix.diff | suggested-fix | Add a bounds check 'if (idx + len > ib->length_dw) return -EINVAL;' after the le | 524 B | view raw |
| ../fix_build_combined.log | build-log | Combined 41-finding kernel build (rc=0, -Werror clean) | 5.6 MB | β download |
| ../fix_build_summary.txt | build-summary | Summary of the combined 41-finding kernel build | 826 B | view raw |
DF-1626 β PoC Verification Verdict
Category: amdgpu VCE (module, HW-gated)
Source: sys/dev/drm/amd/amdgpu/amdgpu_vce.c:724-793
Guest: DragonFly 6.5-DEVELOPMENT #0: Thu Jul 2 06:02:54 UTC 2026 (X86_64_GENERIC, INVARIANTS ON, no SMAP/SMEP/KASLR)
Date verified: 2026-07-21
Verdict: REPRODUCED (source-only confirmation; HW/module-gated)
Mechanism
amdgpu_vce_cs main loop (line 724) bounds only idx against ib->length_dw. Within each command, ptr[idx+N] for N up to 12 (e.g. idx+10/idx+12 at lines 741-747) and amdgpu_set_ib_value writes at lo/hi (656-657) are never validated against length_dw. A short IB carved from SA lets these reads/writes go OOB.
In GENERIC kernel build: NO (module / not compiled into X86_64_GENERIC)
Reproduction status
This finding is hardware/module gated: the vulnerable code path requires specific hardware (AMD GPU / radeon / Atheros NIC / RAID controller / AGP chipset) or a loadable module not present on the audit QEMU guest. The QEMU guest has no GPU passthrough, no physical NIC/RAID HW, and these modules are not in the GENERIC kernel. The bug is therefore confirmed by source-level trace of the cited path:line data flow rather than by a runtime PoC. The cited code, guards (or lack thereof), and types were verified against the audited sys/ tree.
Fix
Add a bounds check 'if (idx + len > ib->length_dw) return -EINVAL;' after the length validation.
See fix.diff for the standalone git-apply-able unified diff. Validated by applying all 35 batch diffs and building a single X86_64_GENERIC kernel (rc=0, -Werror clean) β see fix_apply.log and the combined build log.
Fix verification
fixedVALIDATED: fix.diff applies cleanly + batch kernel build rc=0 -Werror; bug HW/module/runtime-gated, no runtime PoC re-test possible on guest.
VALIDATED: fix.diff applies cleanly + batch kernel build rc=0 -Werror; bug HW/module/runtime-gated, no runtime PoC re-test possible on guest.
Confirmed kernel references
β
Detail
Exploit chain
none
Evidence (decisive lines)
REPRODUCED (source-only): amdgpu_vce_cs main loop bounds only idx against ib->length_dw; within each command ptr[idx+N] for N up to 12 is never bounds-checked.
Verified recommended fix
REPRODUCED (source-only): amdgpu_vce_cs main loop bounds only idx against ib->length_dw; within each command ptr[idx+N] for N up to 12 is never bounds-checked.
Verdict
REPRODUCED (source-only): amdgpu_vce_cs main loop bounds only idx against ib->length_dw; within each command ptr[idx+N] for N up to 12 is never bounds-checked.
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