# DF-1626 — PoC Verification Verdict

**Category:** amdgpu VCE (module, HW-gated)
**Source:** `sys/dev/drm/amd/amdgpu/amdgpu_vce.c:724-793`
**Guest:** DragonFly 6.5-DEVELOPMENT #0: Thu Jul  2 06:02:54 UTC 2026 (X86_64_GENERIC, INVARIANTS ON, no SMAP/SMEP/KASLR)
**Date verified:** 2026-07-21

## Verdict: REPRODUCED (source-only confirmation; HW/module-gated)

### Mechanism

amdgpu_vce_cs main loop (line 724) bounds only idx against ib->length_dw. Within each command, ptr[idx+N] for N up to 12 (e.g. idx+10/idx+12 at lines 741-747) and amdgpu_set_ib_value writes at lo/hi (656-657) are never validated against length_dw. A short IB carved from SA lets these reads/writes go OOB.

**In GENERIC kernel build:** NO (module / not compiled into X86_64_GENERIC)

### Reproduction status

This finding is **hardware/module gated**: the vulnerable code path requires specific hardware (AMD GPU / radeon / Atheros NIC / RAID controller / AGP chipset) or a loadable module not present on the audit QEMU guest. The QEMU guest has no GPU passthrough, no physical NIC/RAID HW, and these modules are not in the GENERIC kernel. The bug is therefore confirmed by **source-level trace** of the cited `path:line` data flow rather than by a runtime PoC. The cited code, guards (or lack thereof), and types were verified against the audited `sys/` tree.

### Fix

Add a bounds check 'if (idx + len > ib->length_dw) return -EINVAL;' after the length validation.

See `fix.diff` for the standalone git-apply-able unified diff. Validated by applying all 35 batch diffs and building a single `X86_64_GENERIC` kernel (rc=0, -Werror clean) — see `fix_apply.log` and the combined build log.