sys/dev/powermng/corepower/corepower.c
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 | /* * Copyright (c) 2015 Imre Vadász <imre@vdsz.com> * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * Device driver for Intel's On Die power usage estimation via MSR. * Supported by Sandy Bridge and later CPUs, and also by Atom CPUs * of the Silvermont and later architectures. */ #include <sys/param.h> #include <sys/bus.h> #include <sys/systm.h> #include <sys/module.h> #include <sys/conf.h> #include <sys/cpu_topology.h> #include <sys/kernel.h> #include <sys/sensors.h> #include <sys/bitops.h> #include <machine/specialreg.h> #include <machine/cpufunc.h> #include <machine/cputypes.h> #include <machine/md_var.h> #include "cpu_if.h" #define MSR_RAPL_POWER_UNIT_POWER __BITS64(0, 3) #define MSR_RAPL_POWER_UNIT_ENERGY __BITS64(8, 12) #define MSR_RAPL_POWER_UNIT_TIME __BITS64(16, 19) struct corepower_sensor { uint64_t energy; u_int msr; struct ksensor sensor; }; struct corepower_softc { device_t sc_dev; uint32_t sc_watt_unit; uint32_t sc_joule_unit; uint32_t sc_second_unit; int sc_have_sens; int sc_is_atom; struct corepower_sensor sc_pkg_sens; struct corepower_sensor sc_dram_sens; struct corepower_sensor sc_pp0_sens; struct corepower_sensor sc_pp1_sens; struct corepower_sensor sc_platform_sens; struct ksensordev sc_sensordev; struct sensor_task *sc_senstask; }; /* * Device methods. */ static void corepower_identify(driver_t *driver, device_t parent); static int corepower_probe(device_t dev); static int corepower_attach(device_t dev); static int corepower_detach(device_t dev); static uint32_t corepower_energy_to_uwatts(struct corepower_softc *sc, uint32_t units, uint32_t secs); static void corepower_refresh(void *arg); static void corepower_sens_init(struct corepower_sensor *sens, char *desc, u_int msr, int cpu); static void corepower_sens_update(struct corepower_softc *sc, struct corepower_sensor *sens); static int corepower_try(u_int msr, char *name); static device_method_t corepower_methods[] = { /* Device interface */ DEVMETHOD(device_identify, corepower_identify), DEVMETHOD(device_probe, corepower_probe), DEVMETHOD(device_attach, corepower_attach), DEVMETHOD(device_detach, corepower_detach), DEVMETHOD_END }; static driver_t corepower_driver = { "corepower", corepower_methods, sizeof(struct corepower_softc), }; static devclass_t corepower_devclass; DRIVER_MODULE(corepower, cpu, corepower_driver, corepower_devclass, NULL, NULL); MODULE_VERSION(corepower, 1); static void corepower_identify(driver_t *driver, device_t parent) { device_t child; const struct cpu_node *node; int cpu, master_cpu; /* Make sure we're not being doubly invoked. */ if (device_find_child(parent, "corepower", -1) != NULL) return; /* Check that the vendor is Intel. */ if (cpu_vendor_id != CPU_VENDOR_INTEL) return; /* We only want one child per CPU package */ cpu = device_get_unit(parent); node = get_cpu_node_by_cpuid(cpu); while (node != NULL) { if (node->type == CHIP_LEVEL) { if (node->child_no == 0) node = NULL; break; } node = node->parent_node; } if (node == NULL) return; master_cpu = BSRCPUMASK(node->members); if (cpu != master_cpu) return; child = device_add_child(parent, "corepower", -1); if (child == NULL) device_printf(parent, "add corepower child failed\n"); } static int corepower_probe(device_t dev) { int cpu_family, cpu_model; if (resource_disabled("corepower", 0)) return (ENXIO); cpu_model = CPUID_TO_MODEL(cpu_id); cpu_family = CPUID_TO_FAMILY(cpu_id); if (cpu_family == 0x06) { switch (cpu_model) { /* Core CPUs */ case 0x2a: case 0x3a: /* Xeon CPUs */ case 0x2d: case 0x3e: case 0x3f: case 0x4f: case 0x56: /* Haswell, Broadwell, Skylake, Kaby Lake, Coffee Lake */ case 0x3c: case 0x3d: case 0x45: case 0x46: case 0x47: case 0x4e: case 0x5e: case 0x8e: /* Kaby Lake, Coffee Lake */ case 0x9e: /* dito */ /* Atom CPUs */ case 0x37: case 0x4a: case 0x4c: case 0x4d: case 0x5a: case 0x5d: break; default: return (ENXIO); } } if (corepower_try(MSR_RAPL_POWER_UNIT, "MSR_RAPL_POWER_UNIT") == 0) return (ENXIO); device_set_desc(dev, "CPU On-Die Power Usage Estimation"); return (BUS_PROBE_GENERIC); } static int corepower_attach(device_t dev) { struct corepower_softc *sc = device_get_softc(dev); uint64_t val; uint32_t power_units; uint32_t energy_units; uint32_t time_units; int cpu_family, cpu_model; int cpu; sc->sc_dev = dev; sc->sc_have_sens = 0; sc->sc_is_atom = 0; cpu_family = CPUID_TO_FAMILY(cpu_id); cpu_model = CPUID_TO_MODEL(cpu_id); /* Check CPU model */ if (cpu_family == 0x06) { switch (cpu_model) { /* Core CPUs */ case 0x2a: case 0x3a: sc->sc_have_sens = 0xd; break; /* Xeon CPUs */ case 0x2d: /* Only Xeon branded, Core i version should probably be 0x5 */ case 0x3e: case 0x3f: case 0x4f: case 0x56: sc->sc_have_sens = 0x7; break; /* Haswell, Broadwell */ case 0x3c: case 0x3d: case 0x45: case 0x46: case 0x47: /* Check if Core or Xeon (Xeon CPUs might be 0x7) */ sc->sc_have_sens = 0xf; break; /* Skylake, Kaby Lake, Coffee Lake */ case 0x4e: case 0x5e: case 0x8e: /* Kaby Lake, Coffee Lake */ case 0x9e: /* dito */ sc->sc_have_sens = 0x1f; break; /* Atom CPUs */ case 0x37: case 0x4a: case 0x4c: case 0x4d: case 0x5a: case 0x5d: sc->sc_have_sens = 0x5; /* use quirk for Valleyview Atom CPUs */ sc->sc_is_atom = 1; break; default: return (ENXIO); } } val = rdmsr(MSR_RAPL_POWER_UNIT); power_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_POWER); energy_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_ENERGY); time_units = __SHIFTOUT(val, MSR_RAPL_POWER_UNIT_TIME); sc->sc_watt_unit = (1 << power_units); sc->sc_joule_unit = (1 << energy_units); sc->sc_second_unit = (1 << time_units); /* * Add hw.sensors.cpu_nodeN MIB. */ cpu = device_get_unit(device_get_parent(dev)); ksnprintf(sc->sc_sensordev.xname, sizeof(sc->sc_sensordev.xname), "cpu_node%d", get_chip_ID(cpu)); if ((sc->sc_have_sens & 1) && corepower_try(MSR_PKG_ENERGY_STATUS, "MSR_PKG_ENERGY_STATUS")) { corepower_sens_init(&sc->sc_pkg_sens, "Package Power", MSR_PKG_ENERGY_STATUS, cpu); sensor_attach(&sc->sc_sensordev, &sc->sc_pkg_sens.sensor); } else { sc->sc_have_sens &= ~1; } if ((sc->sc_have_sens & 2) && corepower_try(MSR_DRAM_ENERGY_STATUS, "MSR_DRAM_ENERGY_STATUS")) { corepower_sens_init(&sc->sc_dram_sens, "DRAM Power", MSR_DRAM_ENERGY_STATUS, cpu); sensor_attach(&sc->sc_sensordev, &sc->sc_dram_sens.sensor); } else { sc->sc_have_sens &= ~2; } if ((sc->sc_have_sens & 4) && corepower_try(MSR_PP0_ENERGY_STATUS, "MSR_PP0_ENERGY_STATUS")) { corepower_sens_init(&sc->sc_pp0_sens, "Cores Power", MSR_PP0_ENERGY_STATUS, cpu); sensor_attach(&sc->sc_sensordev, &sc->sc_pp0_sens.sensor); } else { sc->sc_have_sens &= ~4; } if ((sc->sc_have_sens & 8) && corepower_try(MSR_PP1_ENERGY_STATUS, "MSR_PP1_ENERGY_STATUS")) { corepower_sens_init(&sc->sc_pp1_sens, "Graphics Power", MSR_PP1_ENERGY_STATUS, cpu); sensor_attach(&sc->sc_sensordev, &sc->sc_pp1_sens.sensor); } else { sc->sc_have_sens &= ~8; } if ((sc->sc_have_sens & 0x10) && corepower_try(MSR_PLATFORM_ENERGY_COUNTER, "MSR_PLATFORM_ENERGY_COUNTER") && (rdmsr(MSR_PLATFORM_ENERGY_COUNTER) & 0xffffffffU) != 0) { corepower_sens_init(&sc->sc_platform_sens, "Platform Power", MSR_PLATFORM_ENERGY_COUNTER, cpu); sensor_attach(&sc->sc_sensordev, &sc->sc_platform_sens.sensor); } else { sc->sc_have_sens &= ~0x10; } if (sc->sc_have_sens == 0) return (ENXIO); sc->sc_senstask = sensor_task_register2(sc, corepower_refresh, 1, cpu); sensordev_install(&sc->sc_sensordev); return (0); } static int corepower_detach(device_t dev) { struct corepower_softc *sc = device_get_softc(dev); sensordev_deinstall(&sc->sc_sensordev); sensor_task_unregister2(sc->sc_senstask); return (0); } static uint32_t corepower_energy_to_uwatts(struct corepower_softc *sc, uint32_t units, uint32_t secs) { uint64_t val; if (sc->sc_is_atom) { val = ((uint64_t)units) * sc->sc_joule_unit; } else { val = ((uint64_t)units) * 1000ULL * 1000ULL; val /= sc->sc_joule_unit; } return val / secs; } static void corepower_refresh(void *arg) { struct corepower_softc *sc = (struct corepower_softc *)arg; if (sc->sc_have_sens & 1) corepower_sens_update(sc, &sc->sc_pkg_sens); if (sc->sc_have_sens & 2) corepower_sens_update(sc, &sc->sc_dram_sens); if (sc->sc_have_sens & 4) corepower_sens_update(sc, &sc->sc_pp0_sens); if (sc->sc_have_sens & 8) corepower_sens_update(sc, &sc->sc_pp1_sens); if (sc->sc_have_sens & 0x10) corepower_sens_update(sc, &sc->sc_platform_sens); } static void corepower_sens_init(struct corepower_sensor *sens, char *desc, u_int msr, int cpu) { ksnprintf(sens->sensor.desc, sizeof(sens->sensor.desc), "node%d %s", get_chip_ID(cpu), desc); sens->sensor.type = SENSOR_WATTS; sens->msr = msr; sens->energy = rdmsr(sens->msr) & 0xffffffffU; } static void corepower_sens_update(struct corepower_softc *sc, struct corepower_sensor *sens) { uint64_t a, res; a = rdmsr(sens->msr) & 0xffffffffU; if (sens->energy > a) { res = (0x100000000ULL - sens->energy) + a; } else { res = a - sens->energy; } sens->energy = a; sens->sensor.value = corepower_energy_to_uwatts(sc, res, 1); } static int corepower_try(u_int msr, char *name) { uint64_t val; if (rdmsr_safe(msr, &val) != 0) { kprintf("msr %s (0x%08x) not available\n", name, msr); return 0; } return 1; } |