--- sys/platform/pc64/acpica/acpi_pstate_machdep.c
+++ sys/platform/pc64/acpica/acpi_pstate_machdep.c
@@ -216,13 +216,17 @@ acpi_pst_amd1x_check_pstates1(const stru
 	for (i = 0; i < npstates; ++i) {
 		uint64_t pstate;
 		uint32_t msr;
+		int error;
 
 		msr = msr_start +
 		      (pstates[i].st_cval & AMD_MSR_PSTATE_CSR_MASK);
 		if (msr >= msr_end) {
 			kprintf("cpu%d: MSR P-State register %#08x "
 				"does not exist\n", mycpuid, msr);
 			return EINVAL;
 		}
 
-		pstate = rdmsr(msr);
+		error = rdmsr_safe(msr, &pstate);
+		if (error) {
+			kprintf("cpu%d: MSR P-State register %#08x "
+				"read failed (%d)\n", mycpuid, msr, error);
+			return EINVAL;
+		}
 		if ((pstate & AMD_MSR_PSTATE_EN) == 0) {
@@ -254,10 +258,14 @@ acpi_pst_amd1x_set_pstate(const struct ac
 			  const struct acpi_pstate *pstate)
 {
 	uint64_t cval;
+	int error;
 
 	cval = pstate->st_cval & AMD_MSR_PSTATE_CSR_MASK;
-	wrmsr(AMD1X_MSR_PSTATE_CTL, cval);
+	error = wrmsr_safe(AMD1X_MSR_PSTATE_CTL, cval);
+	if (error)
+		return error;
 
@@ -276,9 +284,13 @@ acpi_pst_amd1x_get_pstate(const struct ac
 			  const struct acpi_pstate *pstates, int npstates)
 {
 	uint64_t sval;
+	int error;
 	int i;
 
-	sval = rdmsr(AMD1X_MSR_PSTATE_ST) & AMD_MSR_PSTATE_CSR_MASK;
+	error = rdmsr_safe(AMD1X_MSR_PSTATE_ST, &sval);
+	if (error)
+		return NULL;
+	sval &= AMD_MSR_PSTATE_CSR_MASK;
@@ -503,15 +515,20 @@ acpi_pst_intel_init(const struct acpi_pst
 	}
 
-	misc_enable = rdmsr(INTEL_MSR_MISC_ENABLE);
-	if ((misc_enable & INTEL_MSR_MISC_EST_EN) == 0) {
+	if (rdmsr_safe(INTEL_MSR_MISC_ENABLE, &misc_enable)) {
+		kprintf("cpu%d: Can't read MISC_ENABLE\n", mycpuid);
+		return EIO;
+	}
+	if ((misc_enable & INTEL_MSR_MISC_EST_EN) == 0) {
 		misc_enable |= INTEL_MSR_MISC_EST_EN;
-		wrmsr(INTEL_MSR_MISC_ENABLE, misc_enable);
+		if (wrmsr_safe(INTEL_MSR_MISC_ENABLE, misc_enable)) {
+			kprintf("cpu%d: Can't enable EST\n", mycpuid);
+			return EIO;
+		}
 
-		misc_enable = rdmsr(INTEL_MSR_MISC_ENABLE);
+		if (rdmsr_safe(INTEL_MSR_MISC_ENABLE, &misc_enable) ||
+		    (misc_enable & INTEL_MSR_MISC_EST_EN) == 0) {
 			kprintf("cpu%d: Can't enable EST\n", mycpuid);
 			return EIO;
 		}
@@ -524,10 +541,17 @@ acpi_pst_intel_set_pstate(const struct ac
 			  const struct acpi_pstate *pstate)
 {
+	uint64_t ctl;
+	int error;
+
 	if (ctrl->pr_res != NULL) {
 		acpi_pst_md_res_write(ctrl, pstate->st_cval);
 	} else {
-		uint64_t ctl;
-
-		ctl = rdmsr(INTEL_MSR_PERF_CTL);
-		ctl &= ~INTEL_MSR_PERF_MASK;
-		ctl |= (pstate->st_cval & INTEL_MSR_PERF_MASK);
-		wrmsr(INTEL_MSR_PERF_CTL, ctl);
+		error = rdmsr_safe(INTEL_MSR_PERF_CTL, &ctl);
+		if (error)
+			return error;
+		ctl &= ~INTEL_MSR_PERF_MASK;
+		ctl |= (pstate->st_cval & INTEL_MSR_PERF_MASK);
+		error = wrmsr_safe(INTEL_MSR_PERF_CTL, ctl);
+		if (error)
+			return error;
 	}
 	return 0;
 }
@@ -543,9 +567,12 @@ acpi_pst_intel_get_pstate(const struct ac
 	} else {
 		uint64_t sval;
 
-		sval = rdmsr(INTEL_MSR_PERF_STATUS) & INTEL_MSR_PERF_MASK;
+		if (rdmsr_safe(INTEL_MSR_PERF_STATUS, &sval))
+			return NULL;
+		sval &= INTEL_MSR_PERF_MASK;