{
  "finding_id": "DF-5345",
  "status": "not_reproduced",
  "reproduced": false,
  "impact": "none",
  "confidence": "certain",
  "verdict": "Code defect certain, panic not observable on stock QEMU 7.2. print_svm_info() executes a raw rdmsr(MSR_AMD_VM_CR) at identcpu.c:1282 (and print_vmx_info()/vmx_settable() read MSR_IA32_FEATURE_CONTROL / MSR_VMX_BASIC / VMX control MSRs raw at :1345,:1350,:1329-1332) gated only on CPUID feature bits the hypervisor controls (:498,:501), with no cpu_exthigh check for leaf 0x8000000A (:1279). Proven on-guest that the path is reached and the unguarded rdmsr executes under a lying CPUID config: TCG boot with -cpu qemu64,+svm,check=off delivered AMD Features2=0x7<LAHF,CMP,SVM> and the kernel printed SVM: Features=0x0 (printed after the rdmsr) then booted to login - QEMU TCG returns 0 for unimplemented MSRs instead of injecting #GP, and under KVM QEMU strips host-unsupported feature bits (SVM bit never reached the guest: AMD Features2=0x1<LAHF>). On hypervisors that fault unsupported MSR reads (KVM semantics; the VirtualBox-class bugs the files own comment at :683-684 documents), the same CPUID lie is a ring-0 #GP during early boot = boot-time kernel panic (unauthenticated machine DoS). The identical class is already mitigated in-file with rdmsr_safe at :689-696 for MSR_IA32_ARCH_CAPABILITIES; these printers never got the same treatment.",
  "exploit_chain": "",
  "evidence": "boot-tcg-svm.log:37 (AMD Features2=0x7<LAHF,CMP,SVM> - CPUID lie delivered), :39 (SVM: Features=0x0 - print_svm_info ran past the rdmsr), :41 (login reached - TCG does not #GP unknown MSRs); boot-kvm-svm-bitstripped.log:37 (KVM control: bit stripped); VERDICT.md (full analysis); contrast identcpu.c:690 rdmsr_safe(MSR_IA32_ARCH_CAPABILITIES)",
  "kernel_refs": [
    "sys/platform/pc64/x86_64/identcpu.c:1279",
    "sys/platform/pc64/x86_64/identcpu.c:1282",
    "sys/platform/pc64/x86_64/identcpu.c:1345",
    "sys/platform/pc64/x86_64/identcpu.c:1350",
    "sys/platform/pc64/x86_64/identcpu.c:1329",
    "sys/platform/pc64/x86_64/identcpu.c:689"
  ],
  "poc_changes": "No seed; authored QEMU-based trigger. KVM variant failed to deliver the SVM bit (QEMU host-feature filtering); switched to TCG where the bit survives - that boot proves path-reachability but TCGs return-0 semantics for unknown MSRs preclude the #GP.",
  "attempts": 2,
  "guest_uname": "DragonFly dfbsd 6.5-DEVELOPMENT #0: Thu Jul  2 06:02:54 UTC 2026 root@dfbsd:/usr/obj/usr/src/sys/X86_64_GENERIC x86_64",
  "runtime_sec": 420,
  "guest_dirty": 0,
  "build_cmd": "(no compile; QEMU boot trigger)",
  "run_cmd": "qemu-system-x86_64 -accel tcg -m 2048 -smp 2 -drive file=ovl-tcgsvm.qcow2,if=virtio,format=qcow2 -cpu qemu64,+svm,check=off -serial file:tcgsvm-boot.log -no-reboot",
  "code_hash": "6fa8637848baf8ca2ebad86c9f97f606eb740c6b0fa34ccda5a9482f4f208bf8",
  "notes": "Panic class requires a hypervisor that injects #GP on unsupported MSR reads while advertising the CPUID bit (KVM does fault, but QEMU refuses to pass the bit on this Intel host; TCG passes the bit but never faults). Same threat class as the in-file ARCH_CAP guard and as DF-5283 (machdep.c MWAIT) - CPUID-advertised feature trusted without capability validation.",
  "recommended_fix": "Use rdmsr_safe() in print_svm_info/print_vmx_info/vmx_settable and skip/print nothing on failure; guard leaf 0x8000000A with cpu_exthigh >= 0x8000000A (see fix.diff)",
  "fix_status": "not_testable",
  "fix_baseline_reproduced": 0,
  "fix_patched_reproduced": 0,
  "fix_verdict": "not_testable: demonstrating the panic before/after the fix requires a hypervisor that advertises VMX/SVM CPUID bits yet faults the MSR reads; stock QEMU 7.2 cannot (TCG returns 0 for unknown MSRs; KVM strips host-unsupported bits). The proposed fix is the identical, in-file-proven pattern (rdmsr_safe) used for MSR_IA32_ARCH_CAPABILITIES at identcpu.c:690.",
  "fix_evidence": "n/a (no faulting hypervisor available); see boot-tcg-svm.log for path-reachability proof"
}