--- a/sys/dev/drm/radeon/uvd_v4_2.c
+++ b/sys/dev/drm/radeon/uvd_v4_2.c
@@ -48,7 +48,19 @@
 	else
 		addr = rdev->uvd.gpu_addr >> 3;
 
-	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 4) >> 3;
+	/*
+	 * Keep offset0+size0 inside the firmware region the bo actually
+	 * holds (RADEON_GPU_PAGE_ALIGN(datasize+8), radeon_uvd.c:184), so
+	 * the HEAP/STACK/SESSION window chain ends at the vcpu_bo boundary
+	 * instead of 512 bytes past it (DF-5229).  Same invariant as amdgpu:
+	 * AMDGPU_UVD_FIRMWARE_OFFSET + AMDGPU_UVD_FIRMWARE_SIZE(adev) ==
+	 * ALIGN(ucode_size+8) (amdgpu_uvd.h:32-38).
+	 */
+	if (rdev->uvd.fw_header_present)
+		size = (RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 8)
+			- 0x200) >> 3;
+	else
+		size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 4) >> 3;
 	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
 	WREG32(UVD_VCPU_CACHE_SIZE0, size);