--- a/sys/dev/powermng/perfbias/perfbias.c
+++ b/sys/dev/powermng/perfbias/perfbias.c
@@ -174,13 +174,24 @@
 {
 	struct perfbias_softc *sc = msg->ch_cbarg;
 	uint64_t hint = msg->ch_cbarg1;
+	int error;
 
-	wrmsr(INTEL_MSR_PERF_BIAS, hint);
-	hint = rdmsr(INTEL_MSR_PERF_BIAS);
+	/*
+	 * NB: some CPUs and VMMs advertise CPUID.06H.ECX bit 3 (SETBH)
+	 * without implementing MSR 0x1b0 -- the same lying-CPUID class
+	 * documented for the thermal bits in coretemp.c.  Use the
+	 * fault-safe accessors so such platforms get an error return
+	 * (EIO to the sysctl writer) instead of a fatal #GP in kernel
+	 * mode.
+	 */
+	error = wrmsr_safe(INTEL_MSR_PERF_BIAS, hint);
+	if (error == 0) {
+		hint = rdmsr(INTEL_MSR_PERF_BIAS);
 
-	sc->sc_hint = hint & INTEL_MSR_PERF_BIAS_HINTMASK;
+		sc->sc_hint = hint & INTEL_MSR_PERF_BIAS_HINTMASK;
+	}
 
-	cpuhelper_replymsg(msg, 0);
+	cpuhelper_replymsg(msg, error);
 }
 
 static int