== amdgpu kmod compiles the dce80 helper:
214:SRCS+= command_table_helper_dce80.c

== which ASICs map to DCE8 (dc_resource.c):

	case FAMILY_CI:
		dc_version = DCE_VERSION_8_0;
		break;
	case FAMILY_KV:
		if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
		    ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
		    ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
			dc_version = DCE_VERSION_8_3;
		else
			dc_version = DCE_VERSION_8_1;
		break;

== who selects the dce80 table (BOTH parser dispatchers):
sys/dev/drm/amd/display/dc/bios/command_table_helper.c-40-	case DCE_VERSION_8_1:
sys/dev/drm/amd/display/dc/bios/command_table_helper.c-41-	case DCE_VERSION_8_3:
sys/dev/drm/amd/display/dc/bios/command_table_helper.c:42:		*h = dal_cmd_tbl_helper_dce80_get_table();
sys/dev/drm/amd/display/dc/bios/command_table_helper.c-43-		return true;
sys/dev/drm/amd/display/dc/bios/command_table_helper.c-44-
sys/dev/drm/amd/display/dc/bios/command_table_helper2.c-41-	case DCE_VERSION_8_1:
sys/dev/drm/amd/display/dc/bios/command_table_helper2.c-42-	case DCE_VERSION_8_3:
sys/dev/drm/amd/display/dc/bios/command_table_helper2.c:43:		*h = dal_cmd_tbl_helper_dce80_get_table();
sys/dev/drm/amd/display/dc/bios/command_table_helper2.c-44-		return true;
sys/dev/drm/amd/display/dc/bios/command_table_helper2.c-45-

== struct command_table_helper: 17 members declared (command_table_helper_struct.h):
17

== dce80 initializer assigns only 15 (the two missing are the last two struct members):
static const struct command_table_helper command_table_helper_funcs = {
	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
	.encoder_action_to_atom = encoder_action_to_atom,
	.engine_bp_to_atom = engine_bp_to_atom,
	.clock_source_id_to_atom = clock_source_id_to_atom,
	.clock_source_id_to_atom_phy_clk_src_id =
		clock_source_id_to_atom_phy_clk_src_id,
	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
	.hpd_sel_to_atom = hpd_sel_to_atom,
	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
	.phy_id_to_atom = phy_id_to_atom,
	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
	.assign_control_parameter =
		dal_cmd_table_helper_assign_control_parameter,
	.clock_source_id_to_ref_clk_src =
		dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
	.transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
	.encoder_mode_bp_to_atom =
		dal_cmd_table_helper_encoder_mode_bp_to_atom,
};

== proof the two members are absent from the dce80 initializer:
0
0 occurrences -> both NULL via designated-initializer zero-fill (C99 6.7.8p10)

== the unguarded consumer call sites:
sys/dev/drm/amd/display/dc/bios/command_table.c:1188:		clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
sys/dev/drm/amd/display/dc/bios/command_table2.c:310:				transmitter_color_depth_to_atom(

== the V7 pixel-clock handler wiring is ROM-revision driven (v1 + v2):
static void init_set_pixel_clock(struct bios_parser *bp)
{
	switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {
	case 3:
		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v3;
		break;
	case 5:
		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v5;
		break;
	case 6:
		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v6;
		break;
	case 7:
		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
		break;
	default:
		dm_output_to_console("Don't have set_pixel_clock for v%d\n",
			 BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock));
		bp->cmd_tbl.set_pixel_clock = NULL;
		break;
	}
static void init_set_pixel_clock(struct bios_parser *bp)
{
	switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {
	case 7:
		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
		break;
	default:
		dm_output_to_console("Don't have set_pixel_clock for v%d\n",
			 BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));
		bp->cmd_tbl.set_pixel_clock = NULL;
		break;
	}
}

== the parser wrapper guards only the rev handler, NOT the helper member:
	struct dc_bios *dcb,
	struct bp_pixel_clock_parameters *bp_params)
{
	struct bios_parser *bp = BP_FROM_DCB(dcb);

	if (!bp->cmd_tbl.set_pixel_clock)
		return BP_RESULT_FAILURE;

	return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
}

== genuine DCE8 VBIOSes are SetPixelClock V6: radeon (same ROM, same command table) implements only V5/V6 and drives all CIK ASICs:
	SET_PIXEL_CLOCK_PS_ALLOCATION base;
	PIXEL_CLOCK_PARAMETERS v1;
	PIXEL_CLOCK_PARAMETERS_V2 v2;
	PIXEL_CLOCK_PARAMETERS_V3 v3;
	PIXEL_CLOCK_PARAMETERS_V5 v5;
	PIXEL_CLOCK_PARAMETERS_V6 v6;
};
radeon has NO V7 path at all -> no genuine DCE8 ROM can report rev 7 (radeon CIK modesetting works)

== contrast: dce112 (the only V7-generation table, DCE11.2+) implements both members:
333:static bool dc_clock_type_to_atom(
358:static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)
401:	.dc_clock_type_to_atom = dc_clock_type_to_atom,
402:	.transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,