# DF-4947 — DCN10 `id_to_offset` hands the I2C pad the DDC6DATA mask (wrong GPIO bit)

**File:** `sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c:211-212,235-237`
**Family:** DF-4944 (dce80 mask-vs-index) — this is the DCN10 twin.
**Severity:** Info · **CWE-697** (plus latent CWE-1298 wrong-bit programming)

## Build

```
gcc -O2 -Wall -Wextra -o harness_mask harness_mask.c
```

## Run

```
./harness_mask
```

## Expected

`id_to_offset(GPIO_ID_DDC_DATA, GPIO_DDC_LINE_I2C_PAD)` pairs
`offset = REG(DC_GPIO_I2CPAD_A)` (0x5dc1) with `mask = 0x100` (the DDC6DATA
bit-8 layout), but `DC_GPIO_I2CPAD_A`'s SDA field is **bit 1 (0x2)**
(dcn_1_0_sh_mask.h:41219) and the factory's own `ddc_i2c_data_regs` entry for
this pin uses that SDA_A_MASK (ddc_regs.h:69-71). Exactly 1 WRONG BIT line;
DDC1-6/VGA (identical bit-8/bit-0 layout to DDC6) and the SCL clock mask are
coincidentally correct. The sole in-tree consumer (`dal_gpio_get_pin_info`,
gpio_base.c:140-147) currently has no callers, so the defect is latent.