===== BASELINE (rv740_dpm.c:166/:259-260 arithmetic verbatim) =====
== DF-4931 replica: rv740_dpm.c clk_v u32-overflow (sclk :166, mclk :259-260) ==
mode: BASELINE (kernel arithmetic verbatim)

[sclk S1 realistic 6%-SS] engine_clock=740000 ref_div=0 post_div=8 ref_clk=27000
  ss.percentage=600 ss.rate=30 -> fbdiv=3592343 clk_s=4500
  numerator 4*pct*fbdiv: exact=8621623200  u32-wrapped=31688608  << WRAPS u32
  clk_v programmed=0   exact=191  (exact FITS the 26-bit field)
  SMC words: SPREAD_SPECTRUM=0x00011941 SPREAD_SPECTRUM_2=0x00000000
  [BUG] SSEN programmed with wrong depth: 0 instead of 191 (off by 191.0x)

[sclk S2 crafted 30%-SS] engine_clock=740000 ref_div=0 post_div=8 ref_clk=27000
  ss.percentage=3000 ss.rate=30 -> fbdiv=3592343 clk_s=4500
  numerator 4*pct*fbdiv: exact=43108116000  u32-wrapped=158443040  << WRAPS u32
  clk_v programmed=3   exact=957  (exact FITS the 26-bit field)
  SMC words: SPREAD_SPECTRUM=0x00011941 SPREAD_SPECTRUM_2=0x00000003
  [BUG] SSEN programmed with wrong depth: 3 instead of 957 (off by 319.0x)

[mclk M1 realistic 2%-SS] memory_clock=80000 ref_clk=10000 decoded_ref=2
  ss.percentage=200 ss.rate=30 whole_fb_div=200 frac=0 -> clk_s=833
  numerator 0x40000*pct*fb: exact=10485760000  u32-wrapped=1895825408  << WRAPS u32
  clk_v programmed=227   exact=1258  (exact FITS the 26-bit field)
  SMC words: MPLL_SS1=0x000000e3 MPLL_SS2=0x00000341
  [BUG] wrong SS depth in MPLL_SS1: 227 instead of 1258 (off by 5.5x)

[mclk M2 realistic 5%-SS] memory_clock=80000 ref_clk=10000 decoded_ref=2
  ss.percentage=500 ss.rate=30 whole_fb_div=200 frac=0 -> clk_s=833
  numerator 0x40000*pct*fb: exact=26214400000  u32-wrapped=444596224  << WRAPS u32
  clk_v programmed=53   exact=3146  (exact FITS the 26-bit field)
  SMC words: MPLL_SS1=0x00000035 MPLL_SS2=0x00000341
  [BUG] wrong SS depth in MPLL_SS1: 53 instead of 3146 (off by 59.4x)

RESULT: 4 SS depth(s) misprogrammed by the u32 numerator wrap
EXIT=98

===== FIXED (64-bit numerators) =====
== DF-4931 replica: rv740_dpm.c clk_v u32-overflow (sclk :166, mclk :259-260) ==
mode: FIXED (64-bit numerators)

[sclk S1 realistic 6%-SS] engine_clock=740000 ref_div=0 post_div=8 ref_clk=27000
  ss.percentage=600 ss.rate=30 -> fbdiv=3592343 clk_s=4500
  numerator 4*pct*fbdiv: exact=8621623200  u32-wrapped=31688608  << WRAPS u32
  clk_v programmed=191   exact=191  (exact FITS the 26-bit field)
  SMC words: SPREAD_SPECTRUM=0x00011941 SPREAD_SPECTRUM_2=0x000000bf

[sclk S2 crafted 30%-SS] engine_clock=740000 ref_div=0 post_div=8 ref_clk=27000
  ss.percentage=3000 ss.rate=30 -> fbdiv=3592343 clk_s=4500
  numerator 4*pct*fbdiv: exact=43108116000  u32-wrapped=158443040  << WRAPS u32
  clk_v programmed=957   exact=957  (exact FITS the 26-bit field)
  SMC words: SPREAD_SPECTRUM=0x00011941 SPREAD_SPECTRUM_2=0x000003bd

[mclk M1 realistic 2%-SS] memory_clock=80000 ref_clk=10000 decoded_ref=2
  ss.percentage=200 ss.rate=30 whole_fb_div=200 frac=0 -> clk_s=833
  numerator 0x40000*pct*fb: exact=10485760000  u32-wrapped=1895825408  << WRAPS u32
  clk_v programmed=1258   exact=1258  (exact FITS the 26-bit field)
  SMC words: MPLL_SS1=0x000004ea MPLL_SS2=0x00000341

[mclk M2 realistic 5%-SS] memory_clock=80000 ref_clk=10000 decoded_ref=2
  ss.percentage=500 ss.rate=30 whole_fb_div=200 frac=0 -> clk_s=833
  numerator 0x40000*pct*fb: exact=26214400000  u32-wrapped=444596224  << WRAPS u32
  clk_v programmed=3146   exact=3146  (exact FITS the 26-bit field)
  SMC words: MPLL_SS1=0x00000c4a MPLL_SS2=0x00000341

RESULT: all programmed depths match the exact 64-bit math
EXIT=0