--- a/sys/dev/drm/radeon/rv740_dpm.c
+++ b/sys/dev/drm/radeon/rv740_dpm.c
@@ -163,14 +163,15 @@
 		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 						     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
 			u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
-			u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
+			u64 clk_v = 4ULL * ss.percentage * fbdiv /
+				((u64)clk_s * 10000);
 
 			cg_spll_spread_spectrum &= ~CLK_S_MASK;
 			cg_spll_spread_spectrum |= CLK_S(clk_s);
 			cg_spll_spread_spectrum |= SSEN;
 
 			cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
-			cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
+			cg_spll_spread_spectrum_2 |= CLK_V((u32)clk_v) & CLK_V_MASK;
 		}
 	}
 
@@ -256,11 +257,12 @@
 			if (!decoded_ref)
 				return -EINVAL;
 			clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
-			clk_v = 0x40000 * ss.percentage *
-				(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
+			clk_v = (u32)(0x40000ULL * ss.percentage *
+				(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) /
+				((u64)clk_s * 10000));
 
 			mpll_ss1 &= ~CLKV_MASK;
-			mpll_ss1 |= CLKV(clk_v);
+			mpll_ss1 |= CLKV(clk_v) & CLKV_MASK;
 
 			mpll_ss2 &= ~CLKS_MASK;
 			mpll_ss2 |= CLKS(clk_s);