/*
 * DF-4887 trigger sketch (NOT runnable — the audit guest has no AMD GPU and
 * the wptr source is device-side DMA into the host writeback buffer).
 *
 * Hostile/faulting-device pattern that arms the two defects in
 * cik_ih_get_wptr (cik_ih.c:186-206):
 *
 * Setup (driver state, from cik_ih_sw_init cik_ih.c:321):
 *   ring_size = 64*1024  => ptr_mask = 0xFFFF, IV = 16 bytes,
 *   adev->irq.ih.wptr_offs = wb slot; ring = 64KiB GTT BO (no slack,
 *   amdgpu_ih.c:80-88).
 *
 * Defect 1 — permanent ithread spin (DF-4843 core, 16-byte grid):
 *   device DMA writes  wptr = 0x0014  (phase 4, no overflow bit)
 *   into adev->wb.wb[wptr_offs].
 *   => amdgpu_ih_process (amdgpu_ih.c:154-157) walks with rptr = 0,16,32,...
 *      (rptr += 16 at cik_ih.c:255/287, masked each step) — phase 0 can
 *      never equal phase 4: 4096 IVs re-dispatched per lap forever,
 *      ih->lock held (amdgpu_ih.c:144), restart_ih re-reads same wptr.
 *
 * Defect 2 — up to 12-byte OOB read past the 64KiB ring BO (DF-4854 shape):
 *   device DMA writes  wptr = 0xFFE4 | RB_OVERFLOW(=1)   (phase 4)
 *   => recovery (cik_ih.c:200): rptr = (0xFFE4 + 16) & 0xFFFF = 0xFFF4
 *   => first prescreen/decode (cik_ih.c:243-246 / 274-277) reads
 *      ring[0x3FFD .. 0x4000]; worst case wptr'=0xFFEF -> rptr=0xFFFF ->
 *      ring[0x3FFF..0x4002] = bytes 0x10000..0x1000B — 12 bytes past the
 *      exact-size GTT BO — decoded as an IV, forwarded to
 *      amdgpu_amdkfd_interrupt (amdgpu_irq.c:170) and dispatched.
 *
 * Expected host behavior if armed on real CIK hardware: amdgpu interrupt
 * thread pegs one CPU forever, all GPU IRQ delivery stops; for defect 2 a
 * one-shot read of whatever follows the ring mapping, consumed as IV data.
 */
int df4887_unused_trigger_placeholder;