--- a/sys/dev/drm/amd/amdgpu/amdgpu_vm.c
+++ b/sys/dev/drm/amd/amdgpu/amdgpu_vm.c
@@ -852,7 +852,14 @@
 	if (r)
 		return r;
 
-	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
+	/*
+	 * The ATS root-PD clear (CHIP_RAVEN) emits TWO set_pte_pde packets
+	 * (2 x 10 dw via vm_pte_funcs->set_pte_pde) and SDMA pad_ib then
+	 * appends up to 7 more dw for 8-dword alignment: 64 bytes (16 dw)
+	 * is not enough -- the emit and pad overran the SA sub-allocation
+	 * by 8 dw (32 bytes).  Size the IB for the worst case.
+	 */
+	r = amdgpu_job_alloc_with_ib(adev, 128, &job);
 	if (r)
 		goto error;
 
@@ -875,7 +882,7 @@
 
 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 
-	WARN_ON(job->ibs[0].length_dw > 64);
+	WARN_ON(job->ibs[0].length_dw > 32);
 	r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
 			     AMDGPU_FENCE_OWNER_UNDEFINED, false);
 	if (r)