########## baseline (unfixed) ##########
===== mode real =====
DF-4858 mode=real (boot mpll_ss=0x00000110 mpll_ss2=0x0bcdef12)
  SS entry matched (vco=3200000 kHz): rate=3000 percentage=20000 -> clk_s=2 clk_v=932
  mpll_ss  =0x000003a5  (CLK_S field=58, expected 2)  [V1: CLK_S CLOBBERED BY clk_v]
  mpll_ss2 =0x08000000  (CLK_V field=0, expected 932)  [V2: CLK_V LOST]  [V3: SSEN with zero SS depth]
VIOLATION V1
VIOLATION V2
  SMC table: vMPLL_SS=0x000003a5 vMPLL_SS2=0x08000000
exit=98
===== mode crafted =====
DF-4858 mode=crafted (boot mpll_ss=0x00000110 mpll_ss2=0x0bcdef12)
  SS entry matched (vco=3200000 kHz): rate=6750 percentage=65535 -> clk_s=1 clk_v=13415
  mpll_ss  =0x00003477  (CLK_S field=839, expected 1)  [V1: CLK_S CLOBBERED BY clk_v]
  mpll_ss2 =0x08000000  (CLK_V field=0, expected 13415)  [V2: CLK_V LOST]  [V3: SSEN with zero SS depth]
VIOLATION V1
VIOLATION V2
  SMC table: vMPLL_SS=0x00003477 vMPLL_SS2=0x08000000
exit=98

########## fixed (-DFIX_DF4858) ##########
===== mode real =====
DF-4858 mode=real (boot mpll_ss=0x00000110 mpll_ss2=0x0bcdef12)
  SS entry matched (vco=3200000 kHz): rate=3000 percentage=20000 -> clk_s=2 clk_v=932
  mpll_ss  =0x00000021  (CLK_S field=2, expected 2)
  mpll_ss2 =0x080003a4  (CLK_V field=932, expected 932)
  SMC table: vMPLL_SS=0x00000021 vMPLL_SS2=0x080003a4
exit=0
===== mode crafted =====
DF-4858 mode=crafted (boot mpll_ss=0x00000110 mpll_ss2=0x0bcdef12)
  SS entry matched (vco=3200000 kHz): rate=6750 percentage=65535 -> clk_s=1 clk_v=13415
  mpll_ss  =0x00000011  (CLK_S field=1, expected 1)
  mpll_ss2 =0x08003467  (CLK_V field=13415, expected 13415)
  SMC table: vMPLL_SS=0x00000011 vMPLL_SS2=0x08003467
exit=0
RUN_DONE