--- a/sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c
+++ b/sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c
@@ -793,13 +793,13 @@ void dce112_compressor_construct(struct dce112_compressor *compressor,
 
 	compressor->base.options.raw = 0;
 	compressor->base.options.bits.FBC_SUPPORT = true;
 	compressor->base.options.bits.LPT_SUPPORT = true;
-	 /* For DCE 11 always use one DRAM channel for LPT */
-	compressor->base.lpt_channels_num = 1;
 	compressor->base.options.bits.DUMMY_BACKEND = false;
+
 	/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
 	 * should not be supported */
+	compressor->base.memory_bus_width = ctx->asic_id.vram_width;
 	if (compressor->base.memory_bus_width == 64)
 		compressor->base.options.bits.LPT_SUPPORT = false;
 
 	compressor->base.options.bits.CLK_GATING_DISABLED = false;
@@ -808,13 +808,12 @@ void dce112_compressor_construct(struct dce112_compressor *compressor,
 	compressor->base.ctx = ctx;
 	compressor->base.embedded_panel_h_size = 0;
 	compressor->base.embedded_panel_v_size = 0;
-	compressor->base.memory_bus_width = ctx->asic_id.vram_width;
 	compressor->base.allocated_size = 0;
 	compressor->base.preferred_requested_size = 0;
 	compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
 	compressor->base.banks_num = 0;
 	compressor->base.raw_size = 0;
 	compressor->base.channel_interleave_size = 0;
 	compressor->base.dram_channels_num = 0;
-	compressor->base.lpt_channels_num = 0;
+	compressor->base.lpt_channels_num = 1;	/* DCE 11: one DRAM channel */
 	compressor->base.attached_inst = 0;
 	compressor->base.is_enabled = false;