sys/dev/drm/amd/amdgpu/amdgpu_vce.h:66:int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
sys/dev/drm/amd/amdgpu/amdgpu_vce.h:67:int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
sys/dev/drm/amd/amdgpu/amdgpu_uvd.h:81:int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx);
sys/dev/drm/amd/amdgpu/amdgpu_ring.h:125:	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
sys/dev/drm/amd/amdgpu/amdgpu_ring.h:126:	int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
sys/dev/drm/amd/amdgpu/amdgpu_ring.h:225:#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
sys/dev/drm/amd/amdgpu/amdgpu_ring.h:226:#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
sys/dev/drm/amd/amdgpu/vce_v4_0.c:1077:	.parse_cs = amdgpu_vce_ring_parse_cs_vm,
sys/dev/drm/amd/amdgpu/vce_v3_0.c:902:	.parse_cs = amdgpu_vce_ring_parse_cs,
sys/dev/drm/amd/amdgpu/vce_v3_0.c:925:	.parse_cs = amdgpu_vce_ring_parse_cs_vm,
sys/dev/drm/amd/amdgpu/vce_v2_0.c:615:	.parse_cs = amdgpu_vce_ring_parse_cs,
sys/dev/drm/amd/amdgpu/uvd_v6_0.c:1530:	.parse_cs = amdgpu_uvd_ring_parse_cs,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c:1266: * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.
sys/dev/drm/amd/amdgpu/uvd_v7_0.c:1272:static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c:1786:	.patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,
sys/dev/drm/amd/amdgpu/uvd_v5_0.c:865:	.parse_cs = amdgpu_uvd_ring_parse_cs,
sys/dev/drm/amd/amdgpu/uvd_v4_2.c:756:	.parse_cs = amdgpu_uvd_ring_parse_cs,
sys/dev/drm/amd/amdgpu/amdgpu_vce.c:708:int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
sys/dev/drm/amd/amdgpu/amdgpu_vce.c:944:int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
sys/dev/drm/amd/amdgpu/amdgpu_uvd.c:964: * amdgpu_uvd_ring_parse_cs - UVD command submission parser
sys/dev/drm/amd/amdgpu/amdgpu_uvd.c:970:int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
sys/dev/drm/amd/amdgpu/amdgpu_cs.c:834:	if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
sys/dev/drm/amd/amdgpu/amdgpu_cs.c:875:			if (ring->funcs->parse_cs) {
sys/dev/drm/amd/amdgpu/amdgpu_cs.c:879:				r = amdgpu_ring_parse_cs(ring, p, j);
sys/dev/drm/amd/amdgpu/amdgpu_cs.c:884:				r = amdgpu_ring_patch_cs_in_place(ring, p, j);
sys/dev/drm/amd/amdgpu/amdgpu_cs.c:1033:		r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
=== vcn_v1_0.c dec ring funcs (2043-2069): NO parse_cs hook ===

static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
	.type = AMDGPU_RING_TYPE_VCN_DEC,
	.align_mask = 0xf,
	.support_64bit_ptrs = false,
	.vmhub = AMDGPU_MMHUB,
	.get_rptr = vcn_v1_0_dec_ring_get_rptr,
	.get_wptr = vcn_v1_0_dec_ring_get_wptr,
	.set_wptr = vcn_v1_0_dec_ring_set_wptr,
	.emit_frame_size =
		6 + 6 + /* hdp invalidate / flush */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
		8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
		14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
		6,
	.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
	.emit_ib = vcn_v1_0_dec_ring_emit_ib,
	.emit_fence = vcn_v1_0_dec_ring_emit_fence,
	.emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
	.test_ring = amdgpu_vcn_dec_ring_test_ring,
	.test_ib = amdgpu_vcn_dec_ring_test_ib,
	.insert_nop = vcn_v1_0_dec_ring_insert_nop,
	.insert_start = vcn_v1_0_dec_ring_insert_start,
	.insert_end = vcn_v1_0_dec_ring_insert_end,
	.pad_ib = amdgpu_ring_generic_pad_ib,
	.begin_use = amdgpu_vcn_ring_begin_use,
=== amdgpu_cs.c:833-836 - ib contents parsed ONLY for rings with parse_cs/patch_cs_in_place ===

	/* Only for UVD/VCE VM emulation */
	if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
		unsigned i, j;

		for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
			struct drm_amdgpu_cs_chunk_ib *chunk_ib;
=== guest runtime: no AMD GPU, no /dev/dri ===