3322 /tmp/psr2_reg_demo.c
BUILD-OK
DF-4450: hsw_activate_psr2() encoding, sink_sync_latency from DPCD
(DP_MAX_RESYNC_FRAME_COUNT_MASK=0xf; HW fields are 4 bits wide)

latency= 7 (typical)               EDP_PSR2_CTL=0xc0000288 -> IDLE_FRAME=8  FRAME_BEFORE_SU=8  TP2_TIME=2500us
latency=11                         EDP_PSR2_CTL=0xc00002cc -> IDLE_FRAME=12  FRAME_BEFORE_SU=12  TP2_TIME=2500us
latency=14 (max legal)             EDP_PSR2_CTL=0xc00002ff -> IDLE_FRAME=15  FRAME_BEFORE_SU=15  TP2_TIME=2500us
latency=15 (SPILLS!)               EDP_PSR2_CTL=0xc0000310 -> IDLE_FRAME=0  FRAME_BEFORE_SU=1  TP2_TIME=50us

With sink_sync_latency=15 the kernel computes idle_frames=16 and
FRAME_BEFORE_SU(16):
  * 16 << 0 spills bit 4 into FRAME_BEFORE_SU (idle reads back 0,
    below the HW minimum of 6 the code tries to enforce)
  * 16 << 4 = 0x100 spills bit 8 into TP2_TIME; OR'ed with the
    requested 2500us encoding (0x200) the field becomes 0x300 = 50us
  -> three independent PSR2 timing fields corrupted in one write