--- a/sys/dev/drm/i915/intel_workarounds.c
+++ b/sys/dev/drm/i915/intel_workarounds.c
@@ -784,7 +784,7 @@
 		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
 		 * enabled subslice, no need to redirect MCR packet
 		 */
-		u32 slice = fls(sseu->slice_mask);
+		u32 slice = ffs(sseu->slice_mask) - 1;
 		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
 		u8 ss_mask = sseu->subslice_mask[slice];
 
--- a/sys/dev/drm/i915/intel_engine_cs.c
+++ b/sys/dev/drm/i915/intel_engine_cs.c
@@ -766,8 +766,8 @@
 {
 	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
 	u32 mcr_s_ss_select;
-	u32 slice = fls(sseu->slice_mask);
-	u32 subslice = fls(sseu->subslice_mask[slice]);
+	u32 slice = ffs(sseu->slice_mask) - 1;
+	u32 subslice = fls(sseu->subslice_mask[slice]) - 1;
 
 	if (INTEL_GEN(dev_priv) == 10)
 		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |