⬢ DragonFlyBSD Kernel Audit
DF-4413 / radeon_abi.h
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/*
 * radeon_abi.h -- self-contained radeon DRM userspace ABI definitions
 * (values copied verbatim from sys/dev/drm/include/uapi/drm/radeon_drm.h,
 *  sys/dev/drm/include/uapi/drm/drm.h; avoids the broken-in-userspace
 *  kernel uapi include chain on DragonFly).
 */
#ifndef RADEON_ABI_H
#define RADEON_ABI_H

#include <stdint.h>
#include <sys/ioccom.h>

#define DRM_IOCTL_BASE	'd'
#define DRM_COMMAND_BASE 0x40

#define DRM_GEM_CLOSE_NR	0x09
#define DRM_GEM_FLINK_NR	0x0a
#define DRM_GEM_OPEN_NR		0x0b

struct drm_gem_close_ { uint32_t handle; uint32_t pad; };
struct drm_gem_flink_ { uint32_t handle; uint32_t pad; uint64_t name; };
struct drm_gem_open_  { uint32_t name; uint32_t pad;
			uint32_t handle; uint32_t size; };

#define DRM_IOCTL_GEM_CLOSE_	_IO(DRM_IOCTL_BASE, DRM_GEM_CLOSE_NR)
#define DRM_IOCTL_GEM_FLINK_	_IOW(DRM_IOCTL_BASE, DRM_GEM_FLINK_NR, struct drm_gem_flink_)
#define DRM_IOCTL_GEM_OPEN_	_IOWR(DRM_IOCTL_BASE, DRM_GEM_OPEN_NR, struct drm_gem_open_)

/* radeon ioctls */
#define DRM_RADEON_GEM_CREATE	0x1d
#define DRM_RADEON_CS		0x26
#define DRM_RADEON_GEM_VA	0x2b

struct drm_radeon_gem_create {
	uint64_t	size;
	uint64_t	alignment;
	uint32_t	handle;
	uint32_t	initial_domain;
	uint32_t	flags;
};

struct drm_radeon_gem_va {
	uint32_t	handle;
	uint32_t	operation;
	uint32_t	vm_id;
	uint32_t	flags;
	uint64_t	offset;
};

struct drm_radeon_cs_chunk {
	uint32_t	chunk_id;
	uint32_t	length_dw;
	uint64_t	chunk_data;
};

struct drm_radeon_cs_reloc {
	uint32_t	handle;
	uint32_t	read_domains;
	uint32_t	write_domain;
	uint32_t	flags;
};

struct drm_radeon_cs {
	uint32_t	num_chunks;
	uint32_t	cs_id;
	uint64_t	chunks;
	uint64_t	gart_limit;
	uint64_t	vram_limit;
};

#define DRM_IOCTL_RADEON_GEM_CREATE_ \
	_IOWR(DRM_IOCTL_BASE, DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, \
	      struct drm_radeon_gem_create)
#define DRM_IOCTL_RADEON_CS_ \
	_IOWR(DRM_IOCTL_BASE, DRM_COMMAND_BASE + DRM_RADEON_CS, \
	      struct drm_radeon_cs)
#define DRM_IOCTL_RADEON_GEM_VA_ \
	_IOWR(DRM_IOCTL_BASE, DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, \
	      struct drm_radeon_gem_va)

#define RADEON_GEM_DOMAIN_GTT		0x2
#define RADEON_GEM_DOMAIN_VRAM		0x4

#define RADEON_VA_MAP			1
#define RADEON_VA_UNMAP			2

#define RADEON_VM_PAGE_READABLE		(1 << 1)
#define RADEON_VM_PAGE_WRITEABLE	(1 << 2)

#define RADEON_CHUNK_ID_RELOCS	0x01
#define RADEON_CHUNK_ID_IB	0x02
#define RADEON_CHUNK_ID_FLAGS	0x03
#define RADEON_CS_USE_VM	0x02

#endif /* RADEON_ABI_H */