--- a/sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -1325,12 +1325,17 @@
 			PP_StateClassificationFlag_Boot))
 		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
 
-	hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);
+	i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);
 
-	if ((i != 0) && (i <= AMD_MAX_VCE_LEVELS)) {
-		for (j = 0; j < i; j++)
-			ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags);
-	}
+	/* hwmgr->vce_states[] holds AMD_MAX_VCE_LEVELS entries: clamp the
+	 * stored count to the array capacity (amdgpu_dpm.c:580 clamps the
+	 * same firmware count for the DPM path). */
+	if (i > AMD_MAX_VCE_LEVELS)
+		i = AMD_MAX_VCE_LEVELS;
+	hwmgr->num_vce_state_tables = i;
+
+	for (j = 0; j < i; j++)
+		ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags);
 
 	return result;
 }