# DF-4348 — undefined shift counts throughout the amdgpu ATOM interpreter (VBIOS-controlled, up to full 32-bit)

`sys/dev/drm/amd/amdgpu/atom.c` uses VBIOS-controlled shift counts
unmasked: `atom_op_shl`/`shr` (atom.c:958/977, full 32-bit operand),
`atom_op_shift_left`/`right` (atom.c:925/941, u8), the WS OR/AND masks
(atom.c:241/244, `gctx->shift` truncated from a u32 write at :508), and
the IIO width masks (atom.c:121-157, `>> (32 - width)` with width 0 or
> 32). Counts ≥ 32 are UB; on the audit guest's gcc 8.3 -O1 the same
expression constant-folds to a different result than runtime x86
masking produces (`0xffff << 40` → 0 vs `0x00ffff00`). Amdgpu twin of
DF-4340 (radeon). Impact: compiler-dependent GPU register values —
hardening/correctness, not memory safety.

## Reproduce (logic level)

```
cc -O1 -g -o atom_harness atom_harness.c
./atom_harness shift   # UB divergence report (exit 0)
```

## Fix

`fix.diff` — `atom_shl`/`atom_shr` (shift ≥ 32 ⇒ 0) at the four op
sites + WS masks; IIO width masks noted as residual.