--- baseline (unmodified REAL dcn_calc_auto.c)
== test dcc: plane0 dcc=yes vs plane1 dcc=no, otherwise identical ==
  read_bw[dcc]=518.400024  read_bw[nodcc]=518.400024  ratio=1.000000000
  DEFECT PRESENT: factor (1 + 1/256) evaluated to exactly 1
  (C integer constant division: 1/256 == 0)
harness rc=1 (1 == defect demonstrated at baseline)
--- fixed (fix.diff applied: float constants)
== test dcc: plane0 dcc=yes vs plane1 dcc=no, otherwise identical ==
  read_bw[dcc]=522.457947  read_bw[nodcc]=520.425049  ratio=1.003906250
  FIXED: factor is (1.0 + 1.0/256.0) = 1.00390625
harness rc=0 (1 == defect demonstrated at baseline)
--- pte-branch isolation (baseline)
== test pte: PTE row overhead factors :181/:184/:187 ==
  4KB_S-vert read_bw=518.400024  var_d-vert read_bw=518.400024 (expect equal:
  (1+1/64) and (1+1/512) both == 1 as compiled)
harness rc=1 (1 == defect demonstrated at baseline)
--- degenerate-input no-trap sweep (baseline)
== degen pixel_clock=0 ==
  [pixel_clock=0] voltage_level=5 (must be 0..5)  mode_support[0][0]=no
  no SIGFPE / no #DE: all divisions are IEEE-754 float
== degen htotal=0 ==
  [htotal=0] voltage_level=5 (must be 0..5)  mode_support[0][0]=no
  no SIGFPE / no #DE: all divisions are IEEE-754 float
== degen zero-socbb-clocks ==
  [zero-socbb-clocks] voltage_level=5 (must be 0..5)  mode_support[0][0]=no
  no SIGFPE / no #DE: all divisions are IEEE-754 float
harness rc=0 (1 == defect demonstrated at baseline)
--- log0 garbage documentation (baseline)
== log0: real dcn_bw_log(0.0f, 2.0f) and dcn_bw_pow garbage ==
  dcn_bw_log(0.0f,2.0f) = -127.0  (dml_log2(0) twin: -127)
  dcn_bw_pow(2.0f, -127.0f) = 5.87747175e-39 (subnormal, no trap)
  [viewport0] voltage_level=5 (must be 0..5)  mode_support[0][0]=no
  dpte path with viewport_width=0: garbage floats only, no trap
harness rc=0 (1 == defect demonstrated at baseline)