--- /home/maxx/dfbsd/dfbsd/sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c	2026-06-29 12:51:18.000000000 +0000
+++ s8_fix4171.c	2026-09-18 09:49:04.516579544 +0000
@@ -454,6 +454,12 @@
 	if (!hwmgr->need_pp_table_upload)
 		return 0;
 
+	if (!vddc_table || !vdd_gfx_table || !acp_table || !uvd_table ||
+	    !vce_table) {
+		pr_err("smu8: missing clock/voltage dependency table(s) in VBIOS powerplay table!\n");
+		return -EINVAL;
+	}
+
 	ret = smum_download_powerplay_table(hwmgr, &table);
 
 	PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
@@ -1257,6 +1263,8 @@
 	/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
 	if (PP_CAP(PHM_PlatformCaps_StablePState) ||
 	    hwmgr->en_umd_pstate) {
+		if (!ptable || ptable->count == 0)
+			return -EINVAL;
 		data->vce_dpm.hard_min_clk =
 				  ptable->entries[ptable->count - 1].ecclk;
 
@@ -1853,6 +1861,8 @@
 		/* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
 		if (PP_CAP(PHM_PlatformCaps_StablePState) ||
 		    hwmgr->en_umd_pstate) {
+			if (!ptable || ptable->count == 0)
+				return -EINVAL;
 			data->uvd_dpm.hard_min_clk =
 				   ptable->entries[ptable->count - 1].vclk;