################ DF-4167 fix A/B (extract from run.log) ################
===== [BASELINE] MODE fw-v32-nosmu =====
[fw-v32-nosmu] firmwareinfo v3.2, dce_refclk_10khz=0, smu_info MISSING (offset 0)
    missing smu_info: GET_IMAGE(.., 0) -> the image base; image bytes [2]=0x10 [3]=0xe0
    revision parsed at image base: major=16 minor=32 -> fallback SKIPPED
    bios_parser_get_firmware_info -> BP_RESULT_OK
    pll_info.crystal_frequency = 0 KHz   <<<<<< ZERO reference clock
    default_engine_clk = 0  default_memory_clk = 200000
    dp_phy_ref_clk = 27000  i2c_engine_ref_clk = 10000
    => DF-4167 CONFIRMED at parser level: OK result with ZERO reference clock
----- rc=1 -----
===== [BASELINE] MODE fw-v32-smu1 =====
[fw-v32-smu1] firmwareinfo v3.2, dce_refclk_10khz=0, smu_info present (rev minor != path)
    bios_parser_get_firmware_info -> BP_RESULT_OK
    pll_info.crystal_frequency = 0 KHz   <<<<<< ZERO reference clock
    default_engine_clk = 0  default_memory_clk = 200000
    dp_phy_ref_clk = 27000  i2c_engine_ref_clk = 10000
    => DF-4167 CONFIRMED at parser level: OK result with ZERO reference clock
----- rc=1 -----
===== [BASELINE] MODE sink-ssdp-post-smu1 =====
[rig] child: entering calculate_pixel_clock_pll_dividers (production dce_clock_source.c:287) ref_freq_khz=0 reference_divider=1 adjusted_pix_clk=154000
[rig] SIGFPE si_code=2 (FPE_INTDIV=2) rip=0x400c27 : inside calculate_fb_and_fractional_fb_divider (dce_clock_source.c:130-170); only zero divisor on this path is ref_freq_khz at :145 div_u64(feedback_divider, ref_freq_khz) => KERNEL EQUIVALENT: #DE PANIC
[sink-ssdp-post-smu1] full chain on identical crafted image (firmwareinfo v3.2, dce_refclk=0, smu_info rev 1 present)
    calc_pll_max_vco_construct -> true, ref_freq_khz=0 max_pll_input=0 min_pll_input=0
    production ranges: calculate_fb_and_fractional_fb_divider=0x400c03..0x400c5d calculate_pixel_clock_pll_dividers=0x400c5d..
    => child exited rc=88 from the SIGFPE handler : DIVIDE-BY-ZERO in production PLL math (kernel: #DE panic)
----- rc=1 -----

################ FIXED (fix.diff) ################
===== [FIXED] MODE fw-v32-nosmu =====
[fw-v32-nosmu] firmwareinfo v3.2, dce_refclk_10khz=0, smu_info MISSING (offset 0)
    missing smu_info: GET_IMAGE(.., 0) -> the image base; image bytes [2]=0x10 [3]=0xe0
    revision parsed at image base: major=16 minor=32 -> fallback SKIPPED
    bios_parser_get_firmware_info -> BP_RESULT_BADBIOSTABLE
    pll_info.crystal_frequency = 0 KHz   <<<<<< ZERO reference clock
    default_engine_clk = 0  default_memory_clk = 0
    dp_phy_ref_clk = 0  i2c_engine_ref_clk = 0
    => parser rejected the table (no zero clock escapes)
----- rc=0 -----
===== [FIXED] MODE fw-v32-smu1 =====
[fw-v32-smu1] firmwareinfo v3.2, dce_refclk_10khz=0, smu_info present (rev minor != path)
    bios_parser_get_firmware_info -> BP_RESULT_OK
    pll_info.crystal_frequency = 27000 KHz
    default_engine_clk = 0  default_memory_clk = 200000
    dp_phy_ref_clk = 27000  i2c_engine_ref_clk = 10000
    => fallback engaged, non-zero reference clock
----- rc=0 -----
===== [FIXED] MODE sink-ssdp-nosmu =====
[sink-ssdp-nosmu] full chain on identical crafted image (firmwareinfo v3.2, dce_refclk=0, smu_info missing)
    calc_pll_max_vco_construct -> false, ref_freq_khz=0 max_pll_input=0 min_pll_input=0
    => clock source construction failed cleanly (parser refused the bad table); no PLL math runs
----- rc=0 -----
===== [FIXED] MODE sink-ssdp-post-smu1 =====
[rig] child: entering calculate_pixel_clock_pll_dividers (production dce_clock_source.c:287) ref_freq_khz=27000 reference_divider=1 adjusted_pix_clk=154000
[sink-ssdp-post-smu1] full chain on identical crafted image (firmwareinfo v3.2, dce_refclk=0, smu_info rev 1 present)
    calc_pll_max_vco_construct -> true, ref_freq_khz=27000 max_pll_input=0 min_pll_input=0
    => reference clock non-zero (27000 KHz); PLL math will not divide by zero
    production ranges: calculate_fb_and_fractional_fb_divider=0x400c03..0x400c5d calculate_pixel_clock_pll_dividers=0x400c5d..
    calculate_pixel_clock_pll_dividers returned 4294967295 (MAX_PLL_CALC_ERROR=4294967295 means no divider found)
    pll_settings: reference_freq=27000 feedback_divider=11 fract_feedback_divider=407407 post_div=2 vco=307998
[sink-ssdp-post-smu1] full chain on identical crafted image (firmwareinfo v3.2, dce_refclk=0, smu_info rev 1 present)
    calc_pll_max_vco_construct -> true, ref_freq_khz=27000 max_pll_input=0 min_pll_input=0
    => reference clock non-zero (27000 KHz); PLL math will not divide by zero
    production ranges: calculate_fb_and_fractional_fb_divider=0x400c03..0x400c5d calculate_pixel_clock_pll_dividers=0x400c5d..
    => child exited rc=0, no divide fault
----- rc=0 -----