--- a/sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
@@ -589,11 +589,19 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 		union firmware_info *firmware_info =
 			(union firmware_info *)(mode_info->atom_context->bios +
 						data_offset);
 		/* pixel clocks */
 		ppll->reference_freq =
 		    le16_to_cpu(firmware_info->info.usReferenceClock);
+		/*
+		 * DF-4153: a zero reference clock reaches unguarded
+		 * divisions in amdgpu_pll.c:92 and atombios_crtc.c:876/879
+		 * (ss step size).  Default to 27 MHz like the other
+		 * limit fixups below.
+		 */
+		if (ppll->reference_freq == 0)
+			ppll->reference_freq = 2700;
 		ppll->reference_div = 0;
@@ -630,10 +638,15 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 		/* system clock */
 		spll->reference_freq =
 			le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
+		/* DF-4153: 0 would divide-by-zero in DPM clock math */
+		if (spll->reference_freq == 0)
+			spll->reference_freq = 10000;
 		spll->reference_div = 0;
@@ -657,10 +670,15 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 		/* memory clock */
 		mpll->reference_freq =
 			le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
+		/* DF-4153: 0 would divide-by-zero in DPM clock math */
+		if (mpll->reference_freq == 0)
+			mpll->reference_freq = 10000;
 		mpll->reference_div = 0;