--- a/sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1141,6 +1141,17 @@
 		timing->v_total > tg110->max_v_total)
 		return false;
 
+	/* Reject timings whose active region plus borders does not fit
+	 * inside the total: the blanking math here and in
+	 * program_blanking would wrap (u32 underflow).
+	 */
+	if (timing->h_addressable == 0 || timing->v_addressable == 0 ||
+		timing->h_total < timing->h_addressable +
+		timing->h_border_left + timing->h_border_right ||
+		timing->v_total < timing->v_addressable +
+		timing->v_border_top + timing->v_border_bottom)
+		return false;
+
 	h_blank = (timing->h_total - timing->h_addressable -
 		timing->h_border_right -
 		timing->h_border_left);
@@ -1151,6 +1162,10 @@
 	if (timing->h_front_porch < tg110->min_h_front_porch)
 		return false;
 
+	if (h_blank < timing->h_front_porch ||
+		timing->h_sync_width > h_blank - timing->h_front_porch)
+		return false;	/* back porch would underflow */
+
 	h_back_porch = h_blank - (h_sync_start -
 		timing->h_addressable -
 		timing->h_border_right -