DF-4038 / fix.diff
--- a/sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c +++ b/sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -1552,7 +1552,7 @@ ro = efuse * (max - min) / 255 + min; /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ - for (i = 0; i < sclk_table->count; i++) { + for (i = 0; i < sclk_table->count && i < NUM_VFT_COLUMNS; i++) { smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= sclk_table->entries[i].cks_enable << i; if (hwmgr->chip_id == CHIP_POLARIS10) { @@ -1571,7 +1571,7 @@ volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + sclk_table->entries[i].cks_voffset) * 100 + 624) / 625); - smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; + smu_data->smc_state_table.Sclk_voltageOffset[i % NUM_VFT_COLUMNS] = volt_offset; } smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6; @@ -1685,7 +1685,7 @@ AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor); AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma); - for (i = 0; i < NUM_VFT_COLUMNS; i++) { + for (i = 0; i < NUM_VFT_COLUMNS && i < sclk_table->count; i++) { AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625); AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100); } |