⬢ DragonFlyBSD Kernel Audit
DF-3940 / fix.diff
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--- a/sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -1305,7 +1305,10 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 	uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
 	uint32_t level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * SMU7_MAX_LEVELS_MEMORY;
 	SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
+	uint32_t mclk_count = min_t(uint32_t, dpm_table->mclk_table.count,
+				    SMU7_MAX_LEVELS_MEMORY);
 	uint32_t i;
 
 	memset(levels, 0x00, level_array_size);
 
-	for (i = 0; i < dpm_table->mclk_table.count; i++) {
+	for (i = 0; i < mclk_count; i++) {
 		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
 			"can not populate memory level as memory clock is zero", return -EINVAL);
 		result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
@@ -1335,9 +1338,10 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
 
-	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
+	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)mclk_count;
 	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
+	smu_data->smc_state_table.MemoryLevel[mclk_count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
 
 	result = ci_copy_bytes_to_smc(hwmgr,
 		level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
 		SMC_RAM_END);
@@ -1791,9 +1795,12 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
 	int result = 0;
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	int res;
-	uint32_t i;
+	uint32_t i, count;
 
-	for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
+	count = min_t(uint32_t, data->dpm_table.mclk_table.count,
+		      SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT);
+
+	for (i = 0; i < count; i++) {
 		res = ci_convert_mc_reg_table_entry_to_smc(
 				hwmgr,
 				data->dpm_table.mclk_table.dpm_levels[i].value,