--- a/sys/dev/drm/amd/amdgpu/dce_v10_0.c
+++ b/sys/dev/drm/amd/amdgpu/dce_v10_0.c
@@ -879,9 +879,17 @@
 	/* First calculate the latency in ns */
 	u32 mc_latency = 2000; /* 2000 ns. */
 	u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
-	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
-	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
-	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
+	u32 worst_chunk_return_time;
+	u32 cursor_line_pair_return_time;
+	u32 dc_latency;
+
+	/* DF-3857: zero bandwidth/clock must not reach the divides below. */
+	if (available_bandwidth == 0 || wm->disp_clk == 0)
+		return 0;
+
+	worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
+	cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
+	dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 		(wm->num_heads * cursor_line_pair_return_time);
 	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
--- a/sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
@@ -678,6 +678,10 @@
 		    le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 		adev->clock.default_mclk =
 		    le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
+		if (adev->clock.default_sclk == 0)
+			adev->clock.default_sclk = 20000;	/* 20 MHz floor */
+		if (adev->clock.default_mclk == 0)
+			adev->clock.default_mclk = 20000;	/* 20 MHz floor */
 
 		mpll->min_post_div = 1;
 		mpll->max_post_div = 1;