# DF-3770 — DFly port dropped the upstream pre-B3 ValleyView PPGTT disable

## Finding
`intel_sanitize_enable_ppgtt()` (`sys/dev/drm/i915/i915_gem_gtt.c:136-183`)
is missing a block present in upstream Linux v4.19 (and earlier, since
3.14):

```c
	/* Early VLV doesn't have this */
	if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) {
		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
		return 0;
	}
```

(verified by direct diff against
raw.githubusercontent.com/torvalds/linux/v4.19 — see `upstream_v419_diff.txt`).

Effect: on ValleyView (Atom Z-series SoC GPU) **pre-B3 silicon** the
DragonFly driver enables PPGTT (aliasing and/or full) where upstream
considers it unsupported. Consequence on that hardware is GPU page
faults / GPU hangs when PPGTT-addressed batches execute — an unprivileged
local user with render-node access can wedge the GPU (recovered only by
the reset machinery). Modern VLV steppings (C0+) are unaffected; all
other platforms are unaffected. No memory-safety consequence: the
PPGTT walkers themselves are bounds-correct; this is an enable-bit
divergence only.

Filed as **Info** (upstream-divergence record): the removal appears to be
an accidental trim during the port rather than a deliberate decision (no
commit message rationale; the block is silent in the DFly diff).

## Fix
Restore the upstream block — see `fix.diff`.

## Reproduction
Requires an actual pre-B3 ValleyView part; the audit guest is virtio-only
(no Intel GPU at all — `pciconf` shows 0x1111:1234; no i915kms.ko).
Runtime verification skipped per contract.