--- a/sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4122,7 +4122,8 @@ static void vega10_get_sclks(struct pp_h
 	clocks->num_levels = 0;
-	for (i = 0; i < dep_table->count; i++) {
+	for (i = 0; i < dep_table->count && i < PP_MAX_CLOCK_LEVELS; i++) {
 		if (dep_table->entries[i].clk) {
 			clocks->data[clocks->num_levels].clocks_in_khz =
 					dep_table->entries[i].clk * 10;
@@ -4143,7 +4144,8 @@ static void vega10_get_memclocks(struct
 	uint32_t j = 0;
 	uint32_t i;
 
-	for (i = 0; i < dep_table->count; i++) {
+	/* data[] is PP_MAX_CLOCK_LEVELS; mclk_latency_table.entries[] is 8 */
+	for (i = 0; i < dep_table->count && i < PP_MAX_CLOCK_LEVELS; i++) {
 		if (dep_table->entries[i].clk) {
 
 			clocks->data[j].clocks_in_khz =
@@ -4167,7 +4169,8 @@ static void vega10_get_dcefclocks(struct
 	uint32_t i;
 
-	for (i = 0; i < dep_table->count; i++) {
+	clocks->num_levels = 0;
+	for (i = 0; i < dep_table->count && i < PP_MAX_CLOCK_LEVELS; i++) {
 		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
 		clocks->data[i].latency_in_us = 0;
 		clocks->num_levels++;
@@ -4183,7 +4186,8 @@ static void vega10_get_socclocks(struct
 	uint32_t i;
 
-	for (i = 0; i < dep_table->count; i++) {
+	clocks->num_levels = 0;
+	for (i = 0; i < dep_table->count && i < PP_MAX_CLOCK_LEVELS; i++) {
 		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
 		clocks->data[i].latency_in_us = 0;
 		clocks->num_levels++;
@@ -4243,7 +4247,8 @@ static int vega10_get_clock_by_type_with_
 	}
 
-	for (i = 0; i < dep_table->count; i++) {
+	clocks->num_levels = 0;
+	for (i = 0; i < dep_table->count && i < PP_MAX_CLOCK_LEVELS; i++) {
 		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
 		clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
 				entries[dep_table->entries[i].vddInd].us_vdd);