--- a/sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4425,7 +4425,7 @@
 		}
 		now = i;
 
-		for (i = 0; i < sclk_table->count; i++)
+		for (i = 0; i < sclk_table->count && i < MAX_REGULAR_DPM_NUMBER; i++)
 			size += sprintf(buf + size, "%d: %uMhz %s\n",
 					i, sclk_table->dpm_levels[i].value / 100,
 					(i == now) ? "*" : "");
@@ -4441,7 +4441,7 @@
 		}
 		now = i;
 
-		for (i = 0; i < mclk_table->count; i++)
+		for (i = 0; i < mclk_table->count && i < MAX_REGULAR_DPM_NUMBER; i++)
 			size += sprintf(buf + size, "%d: %uMhz %s\n",
 					i, mclk_table->dpm_levels[i].value / 100,
 					(i == now) ? "*" : "");
@@ -4455,7 +4455,7 @@
 		}
 		now = i;
 
-		for (i = 0; i < pcie_table->count; i++)
+		for (i = 0; i < pcie_table->count && i < MAX_REGULAR_DPM_NUMBER; i++)
 			size += sprintf(buf + size, "%d: %s %s\n", i,
 					(pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
 					(pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
@@ -4465,7 +4465,8 @@
 	case OD_SCLK:
 		if (hwmgr->od_enabled) {
 			size = sprintf(buf, "%s:\n", "OD_SCLK");
-			for (i = 0; i < odn_sclk_table->num_of_pl; i++)
+			for (i = 0; i < odn_sclk_table->num_of_pl &&
+					i < MAX_REGULAR_DPM_NUMBER; i++)
 				size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
 					i, odn_sclk_table->entries[i].clock/100,
 					odn_sclk_table->entries[i].vddc);
@@ -4474,7 +4475,8 @@
 	case OD_MCLK:
 		if (hwmgr->od_enabled) {
 			size = sprintf(buf, "%s:\n", "OD_MCLK");
-			for (i = 0; i < odn_mclk_table->num_of_pl; i++)
+			for (i = 0; i < odn_mclk_table->num_of_pl &&
+					i < MAX_REGULAR_DPM_NUMBER; i++)
 				size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
 					i, odn_mclk_table->entries[i].clock/100,
 					odn_mclk_table->entries[i].vddc);