--- a/sys/dev/drm/radeon/ci_dpm.c
+++ b/sys/dev/drm/radeon/ci_dpm.c
@@ -2862,6 +2862,11 @@ static int ci_calculate_mclk_params(struct radeon_device *rdev,
 		u32 tmp;
 		u32 reference_clock = rdev->clock.mpll.reference_freq;
 
+		if (reference_clock == 0) {
+			DRM_ERROR("invalid mpll reference clock\n");
+			return -EINVAL;
+		}
+
 		if (mpll_param.qdr == 1)
 			freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
 		else
@@ -3200,6 +3205,12 @@ static int ci_calculate_sclk_params(struct radeon_device *rdev,
 	if (pi->caps_sclk_ss_support) {
 		struct radeon_atom_ss ss;
 		u32 vco_freq = engine_clock * dividers.post_div;
 
+		if (reference_clock == 0) {
+			DRM_ERROR("invalid spll reference clock\n");
+			return -EINVAL;
+		}
 		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 						     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {