--- a/sys/dev/drm/radeon/ci_dpm.c
+++ b/sys/dev/drm/radeon/ci_dpm.c
@@ -2872,6 +2872,10 @@ static int ci_calculate_mclk_params(struct radeon_device *rdev,
 		tmp = (freq_nom / reference_clock);
 		tmp = tmp * tmp;
 		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 						     ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
+			if (ss.rate == 0) {
+				DRM_ERROR("invalid SS rate for mclk\n");
+				return -EINVAL;
+			}
 			u32 clks = reference_clock * 5 / ss.rate;
 			u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
 
@@ -3222,6 +3226,11 @@ static int ci_calculate_sclk_params(struct radeon_device *rdev,
 		u32 vco_freq = engine_clock * dividers.post_div;
 
 		if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 						     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
+			if (ss.rate == 0) {
+				DRM_ERROR("invalid SS rate for sclk\n");
+				return -EINVAL;
+			}
 			u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
 			u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);