dfrig_cyx[go1]: BEFORE dispatch: ch->dma=0xffffffff82601040 ctlr->r_res1=0xffffffff82601820 (guard ata-cyrix.c:84 passes) atadev->unit=0
dfrig_cyx[go1]: dispatching production ata_cyrix_setmode(dev, 0x0f) (RUNNING KERNEL own copy)
dfrig_cyx[go1]: RETURNED: ch->dma->alignment=16 max_iosize=32768
dfrig_cyx[go1]: requested mode=0x0f settled mode=0x0c controlcmd_seen=1
dfrig_cyx[go1]: INDEX USED  = mode & ATA_MODE_MASK = 0x0c & 0x0f = 12   (piotiming[] has 5 elements: 0..4)  <<< OUT OF BOUNDS
dfrig_cyx[go1]: INDEX RIGHT = ata_mode2idx(mode)   = 4   (the idiom every sibling uses)
dfrig_cyx[go1]: CORRECT VALUE piotiming[4] = 0x00040010 (source constant)
dfrig_cyx[go1]: controller register file (fabricated BMIO MEM space):
dfrig_cyx[go1]:   reg 0x20 (PIO timing, devno 0)  = 0x00040010
dfrig_cyx[go1]:   reg 0x24 (DMA timing, devno 0)  = 0x00000000
dfrig_cyx[go1]: OOB SOURCE kernel_mem[piotiming+12*4] = 0x00911030  (MISMATCH vs reg 0x20?!)
dfrig_cyx[go2]: BEFORE dispatch: ch->dma=0xffffffff82601040 ctlr->r_res1=0xffffffff82601820 (guard ata-cyrix.c:84 passes) atadev->unit=0
dfrig_cyx[go2]: dispatching production ata_cyrix_setmode(dev, 0x0f) (verbatim #included copy)
dfrig_cyx[go2]: RETURNED: ch->dma->alignment=16 max_iosize=32768
dfrig_cyx[go2]: requested mode=0x0f settled mode=0x0c controlcmd_seen=1
dfrig_cyx[go2]: INDEX USED  = mode & ATA_MODE_MASK = 0x0c & 0x0f = 12   (piotiming[] has 5 elements: 0..4)  <<< OUT OF BOUNDS
dfrig_cyx[go2]: INDEX RIGHT = ata_mode2idx(mode)   = 4   (the idiom every sibling uses)
dfrig_cyx[go2]: CORRECT VALUE piotiming[4] = 0x00040010 (source constant)
dfrig_cyx[go2]: controller register file (fabricated BMIO MEM space):
dfrig_cyx[go2]:   reg 0x20 (PIO timing, devno 0)  = 0x00040010
dfrig_cyx[go2]:   reg 0x24 (DMA timing, devno 0)  = 0x00000000
dfrig_cyx[go2]: OOB SOURCE kernel_mem[piotiming+12*4] = 0x00911030  (MISMATCH vs reg 0x20?!)
dfrig_cyx[go3]: BEFORE dispatch: ch->dma=0xffffffff82601040 ctlr->r_res1=0xffffffff82601820 (guard ata-cyrix.c:84 passes) atadev->unit=0
dfrig_cyx[go3]: dispatching production ata_cyrix_setmode(dev, 0x0f) (RUNNING KERNEL own copy)
dfrig_cyx[go3]: RETURNED: ch->dma->alignment=16 max_iosize=32768
dfrig_cyx[go3]: requested mode=0x0f settled mode=0x08 controlcmd_seen=1
dfrig_cyx[go3]: INDEX USED  = mode & ATA_MODE_MASK = 0x08 & 0x0f = 8   (piotiming[] has 5 elements: 0..4)  <<< OUT OF BOUNDS
dfrig_cyx[go3]: INDEX RIGHT = ata_mode2idx(mode)   = 0   (the idiom every sibling uses)
dfrig_cyx[go3]: CORRECT VALUE piotiming[0] = 0x00009172 (source constant)
dfrig_cyx[go3]: controller register file (fabricated BMIO MEM space):
dfrig_cyx[go3]:   reg 0x20 (PIO timing, devno 0)  = 0x00009172
dfrig_cyx[go3]:   reg 0x24 (DMA timing, devno 0)  = 0x00000000
dfrig_cyx[go3]: OOB SOURCE kernel_mem[piotiming+8*4] = 0x00002020  (MISMATCH vs reg 0x20?!)
dfrig_cyx[go4]: BEFORE: requested mode=ATA_UDMA2 -- full extracted call site ata-pci.c:855-866 (call1 = ctlr->setmode(dev, ATA_PIO_MAX), call2 = ctlr->setmode(dev, 0x42))
dfrig_cyx[go4]: RETURNED: alignment=16 max_iosize=32768 controlcmd_seen=2 (2 SETXFER = normal)
dfrig_cyx[go4]: requested mode=0x42 settled mode=0x42 controlcmd_seen=2
dfrig_cyx[go4]: INDEX USED  = mode & ATA_MODE_MASK = 0x42 & 0x0f = 2   (piotiming[] has 5 elements: 0..4)
dfrig_cyx[go4]: controller register file (fabricated BMIO MEM space):
dfrig_cyx[go4]:   reg 0x20 (PIO timing, devno 0)  = 0x00040010
dfrig_cyx[go4]:   reg 0x24 (DMA timing, devno 0)  = 0x00911030
dfrig_cyx[go5]: BEFORE dispatch: ch->dma=0xffffffff82601040 ctlr->r_res1=0xffffffff82601820 (guard ata-cyrix.c:84 passes) atadev->unit=0
dfrig_cyx[go5]: dispatching production ata_cyrix_setmode(dev, 0x22) (RUNNING KERNEL own copy)
dfrig_cyx[go5]: RETURNED: ch->dma->alignment=16 max_iosize=32768
dfrig_cyx[go5]: requested mode=0x22 settled mode=0x22 controlcmd_seen=1
dfrig_cyx[go5]: INDEX USED  = mode & ATA_MODE_MASK = 0x22 & 0x0f = 2   (piotiming[] has 5 elements: 0..4)
dfrig_cyx[go5]: controller register file (fabricated BMIO MEM space):
dfrig_cyx[go5]:   reg 0x20 (PIO timing, devno 0)  = 0x00000000
dfrig_cyx[go5]:   reg 0x24 (DMA timing, devno 0)  = 0x00002020