# DF-1693 — PoC Verification Verdict

**Category:** amdgpu debugfs (module, HW-gated)
**Source:** `sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c:229-452`
**Guest:** DragonFly 6.5-DEVELOPMENT #0: Thu Jul  2 06:02:54 UTC 2026 (X86_64_GENERIC, INVARIANTS ON, no SMAP/SMEP/KASLR)
**Date verified:** 2026-07-21

## Verdict: REPRODUCED (source-only confirmation; HW/module-gated)

### Mechanism

amdgpu_debugfs_regs_pcie/didt/smc _read/_write handlers pass user-supplied *pos directly to RREG32_*/WREG32_* MMIO accessors with no upper-bound check. amdgpu_debugfs_regs_pcie_read:242 value=RREG32_PCIE(*pos >> 2). An arbitrary *pos causes arbitrary MMIO read/write (information leak / hardware state corruption).

**In GENERIC kernel build:** NO (module / not compiled into X86_64_GENERIC)

### Reproduction status

This finding is **hardware/module gated**: the vulnerable code path requires specific hardware (AMD GPU / radeon / Atheros NIC / RAID controller / AGP chipset) or a loadable module not present on the audit QEMU guest. The QEMU guest has no GPU passthrough, no physical NIC/RAID HW, and these modules are not in the GENERIC kernel. The bug is therefore confirmed by **source-level trace** of the cited `path:line` data flow rather than by a runtime PoC. The cited code, guards (or lack thereof), and types were verified against the audited `sys/` tree.

### Fix

Add upper-bound validation on *pos against the device's register space (e.g. adev->gmc.mc_vram_size) before the MMIO accessor call.

See `fix.diff` for the standalone git-apply-able unified diff. Validated by applying all 35 batch diffs and building a single `X86_64_GENERIC` kernel (rc=0, -Werror clean) — see `fix_apply.log` and the combined build log.