⬢ DragonFlyBSD Kernel Audit
DF-1166 / fix.diff
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diff --git a/sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
--- a/sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -688,7 +688,8 @@
 	/* Initialize Sclk DPM table based on allow Sclk values*/
 	data->dpm_table.sclk_table.count = 0;
 
-	for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
+	for (i = 0; i < allowed_vdd_sclk_table->count &&
+	     i < MAX_REGULAR_DPM_NUMBER; i++) {
 		if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
 				allowed_vdd_sclk_table->entries[i].clk) {
 			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
@@ -702,7 +703,8 @@
 		"MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 	/* Initialize Mclk DPM table based on allow Mclk values */
 	data->dpm_table.mclk_table.count = 0;
-	for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
+	for (i = 0; i < allowed_vdd_mclk_table->count &&
+	     i < MAX_REGULAR_DPM_NUMBER; i++) {
 		if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
 			allowed_vdd_mclk_table->entries[i].clk) {
 			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
@@ -713,23 +715,29 @@
 	}
 
 	/* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
-	for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
+	for (i = 0; i < allowed_vdd_sclk_table->count &&
+	     i < MAX_REGULAR_DPM_NUMBER; i++) {
 		data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 		data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
 		/* param1 is for corresponding std voltage */
 		data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
 	}
 
-	data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
+	data->dpm_table.vddc_table.count =
+		(allowed_vdd_sclk_table->count <= MAX_REGULAR_DPM_NUMBER) ?
+		allowed_vdd_sclk_table->count : MAX_REGULAR_DPM_NUMBER;
 	allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
 
 	if (NULL != allowed_vdd_mclk_table) {
 		/* Initialize Vddci DPM table based on allow Mclk values */
-		for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
+		for (i = 0; i < allowed_vdd_mclk_table->count &&
+		     i < MAX_REGULAR_DPM_NUMBER; i++) {
 			data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 			data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
 		}
-		data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
+		data->dpm_table.vddci_table.count =
+			(allowed_vdd_mclk_table->count <= MAX_REGULAR_DPM_NUMBER) ?
+			allowed_vdd_mclk_table->count : MAX_REGULAR_DPM_NUMBER;
 	}
 
 	allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
@@ -739,11 +747,14 @@
 		 * Initialize MVDD DPM table based on allow Mclk
 		 * values
 		 */
-		for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
+		for (i = 0; i < allowed_vdd_mclk_table->count &&
+		     i < MAX_REGULAR_DPM_NUMBER; i++) {
 			data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 			data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
 		}
-		data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
+		data->dpm_table.mvdd_table.count =
+			(allowed_vdd_mclk_table->count <= MAX_REGULAR_DPM_NUMBER) ?
+			allowed_vdd_mclk_table->count : MAX_REGULAR_DPM_NUMBER;
 	}
 
 	return 0;
@@ -781,7 +792,8 @@
 
 	/* Initialize Sclk DPM table based on allow Sclk values */
 	data->dpm_table.sclk_table.count = 0;
-	for (i = 0; i < dep_sclk_table->count; i++) {
+	for (i = 0; i < dep_sclk_table->count &&
+	     i < MAX_REGULAR_DPM_NUMBER; i++) {
 		if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 						dep_sclk_table->entries[i].clk) {
 
@@ -797,7 +809,8 @@
 		hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
 	/* Initialize Mclk DPM table based on allow Mclk values */
 	data->dpm_table.mclk_table.count = 0;
-	for (i = 0; i < dep_mclk_table->count; i++) {
+	for (i = 0; i < dep_mclk_table->count &&
+	     i < MAX_REGULAR_DPM_NUMBER; i++) {
 		if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 				[data->dpm_table.mclk_table.count - 1].value !=
 						dep_mclk_table->entries[i].clk) {